The sub-threshold and gate leakage power consumption in deep submicron CMOS systems are projected to become a significant part of the total power dissipation. This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance. A dual-mode logic gate, for selectable operation in either of static and dynamic modes, includes: a static gate which includes at least one logic input and a logic output; a mode selector, configured for outputting a turn-off signal to select static mode operation and for outputting a dynamic clock signal to select dynamic mode operation and a switching element associated with the mode selector static gate, comprising a first input connected to a constant voltage, a second input for inputting the mode selection signal from the mode selector, and an output connected to a logic output of the static gate. The switching elements switches the logic gate operation from static to dynamic mode, by applying the appropriate signal to the switching element. As transistor sizes scale down and levels of integration increase, leakage power has become a critical problem in VLSI designs. In this paper, an industry-standard technique known as power-gating is explored, whereby transistors are used to disconnect the power from idle portions of a chip.This paper discusses the evolution of full adder circuits in terms of lesser power consumption high speed. The power gating techniques are implemented to design a full adder by reducing the number of transistors which also leads to the reduction of chip size.
Keywords: Dual Mode Logic, Sub-threshold, Power Gating
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